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Flight Processor Emulators

Flight Processor Emulators are an essential part of satellite simulators – both for testing of flight software and at the heart of operational simulators.


What we do

The Terma Emulator is a suite of instruction-level emulators, based in the LLVM framework, supporting several processors used in the Space industry:

  • ERC32 in both 3-chips configuration (691-E) and single chip configuration (695-F).
  • LEON 2 (AT-697F) along with the standard peripheral devices: UARTs, GPIO, etc.
  • LEON 3 (UT-699, but can be reconfigured by the user to implement other CPU cores) along with the standard peripheral devices which are part of GRLIB: timers, UARTs, memory controller, GPIO, etc. A high performance model of the SRMMU is included.
  • LEON4 including peripherals and SRMMU.
  • ARM support.

The Emulator suite is not restricted to these pre-configured systems. The flexibility of the Terma Emulator design allows for the tailoring of many configurations, including the ability of adding user-defined models or to replace some of the "standard" models with customized ones.

The Emulator can also be used as the core of a simulation kernel, with the simulations models being scheduled by the emulator itself.

Artist's impression of ESA's PLATO spacecraft ESA
ESA’s planet hunter

The PLATO Mission

The objective of PLATO (PLAnetary Transits and Oscillations of stars) is to find and study a large number of extrasolar planetary systems, with emphasis on the properties of terrestrial planets in the habitable zone around solar-like stars. PLATO has also been designed to investigate seismic activity in stars, enabling the precise characterisation of the planet host star, including its age. The flight software for PLATO is developed using the our TEMU Emulator.


Designed for performance

The LLVM based emulator core is highly optimised with different instruction variants, threaded code, and many other sophisticated optimisations. The emulator is prepared for integrating more high performing emulation methods such as binary translation.

Instruction-level emulation accuracy

Specifically designed to cover the needs of S/C simulators, but also capable of running in Real-Time environments like Software Validation Facilities and other kind of real-time simulators. The emulator also allow for the integration of cache models for detailed performance and timing analysis.

Highly customisable

Almost any desired customization is possible through the tailoring mechanisms provided by the Terma Emulator Suite. CPU configurations can be adapted by picking and mapping in different device models as needed.


The emulator has a public API for implementing native device models but can easily be integrated with other device modeling systems (e.g. SMP2, System-C and others). The emulator has also been designed to allow for additional target architectures (in addition to the SPARCv8 supported at the moment). Any RISC-like (fixed width) instruction-set can be added with relative ease, other non-RISC instruction sets can be supported if needed as well.

Not restricted to any particular simulation infrastructure

The Terma Emulator Suite is designed to be usable in different simulation frameworks, including the ESOC simulation framework, which is based on SIMSAT. It is even possible to mimic the interface of other emulation solutions, making it possible to develop emulator-solution independent simulators. It is also possible to implement a whole simulator inside the T-EMU framework.

User friendly

A fully functional command line test harness program provides complete visibility of the emulation to the users. Interactive commands allow the inspection and modification of the memory and emulated registers, assembly and disassembly of instructions, setting of breakpoints and watch points, etc.

Debug variants available

The emulator comes in two versions which can be installed at the same time. A normal release version, and a debug version with asserts enabled. The debug version is helpful during simulator integration, but you do not have to pay the performance penalty of runtime asserts if you do not want to.

Exhaustive and fully automated test suite enabling nightly builds

Each instruction is extensively tested to cover a wide range of possible operands and combinations. The test-suite includes not only instruction tests and functionality, but also real-world uses such as booting the Linux kernel. The tests are executed nightly and you can rest assured that nightly builds made available are passing the whole test-suite.

Multi-core and multi-system emulation

Supported out of the box by the Terma Emulator. The several emulator cores can be run in a fully deterministic manner. It is also possible to run separate computer models in parallel, instantiated from the same configuration.


The emulator supports x86-64 Linux at the moment, but other POSIX (GNU/Linux, BSD, Solaris, Darwin) systems can easily be supported, even Windows support can be made available if requested.

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The Terma Emulator can be used in two main ways:

  • Linked with the command line test harness, providing a standalone binary which provides the emulation and simulation environment.
  • As a shared library that can be combined or loaded in the corresponding simulation infrastructure or model.

Contact us

If you have any questions about our Emulators, please send us a message.

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Søren Pedersen SPDS

Director, Sales and Business Development

Søren Pedersen