TEMU - Spacecraft Flight Processor Emulators
Build and test your spacecraft’s onboard software in a realistic, virtual environment with a flight processor emulator —fully modeled, hardware-free, and fully configurable.
Validate Flight Software with TEMU, Flight Processor Emulator
Terma Emulator (TEMU) is Terma’s processor emulator and full system simulator for spacecraft software development, debugging, and verification. It enables you to run your actual flight code in a full system simulation—without modifying binaries or relying on real hardware. Whether you're debugging software during early development or running regression tests late in the project, TEMU delivers the accuracy, speed, and flexibility needed to keep your mission on track. It supports standalone operation or integration into existing simulator setups, giving engineers full control over their validation process.
You can embed TEMU into a full simulator setup, use it as your main simulation environment, or connect it to your test automation system. With support for SPARC (ERC32, LEON2/3/4/5), PowerPC (e500), ARM (Cortex-R5), and RISC-V (NOEL-V), TEMU provides the performance, precision, and adaptability modern space missions require. You catch issues early, validate faster, and save time across your project.
Run real flight code by using unmodified flight software binaries, with precise CPU behavior and a full I/O model library.
Simulate processors, memory, devices, and buses in a single tool—no external hardware required.
Configure devices, memory, CPUs, and system behaviors with mission-specific extensions and native APIs.
TEMU: SPACECRAFT EMULATOR
TEMU is a suite of instruction-level emulators, supporting several processors used in the space industry:
- SPARC
- ERC32 (TSC691E, TSC695F)
- LEON2 (AT697E, AT697F) along with the standard peripheral devices: UARTs, GPIO, etc.
- LEON3 (UT699, UT700, GR712RC)
- LEON4 (GR740)
- LEON5 (GR765)
- PowerPC
- e500 (P2010, P2020)
- ARM
- Cortex-R5 (TMS570)
- RISC-V
- NOEL-V (GR765)
Note that TEMU emulator is not restricted to these pre-configured systems. The flexibility of the Terma Emulator design allows for the tailoring of many configurations, including the ability of adding user-defined models or to replace some of the "standard" models with customized ones.
The Emulator can also be used as the core of a simulation kernel, with the simulation models being scheduled by the emulator itself.
FEATURES
High-Performance Emulator Cores
TEMU uses the LLVM toolchain and dynamic binary translation to reach high-speed execution—supporting real-time and faster-than-real-time software simulation.
Multi-Core and Multi-Processor Support
Built for modern flight computers like the GR712RC and GR740, TEMU handles multi-core systems with synchronized execution and accurate timing models.
Built-In Device and Bus Models
Start simulation quickly with included models for standard spacecraft buses and devices. Avoid the overhead of building everything from scratch.
Advanced Memory Modeling
Simulate fast address decoding, add custom cache models, and model full memory behavior for better performance analysis and fault injection.
Custom Modeling API
Create your own device models using the C-based API. Inspect registers, map memory, snapshot system state, and extend functionality—all scriptable and testable.
Python Scripting Integration
Easily wrap the modeling API for Python and other scripting tools. Build test automation pipelines and run batch simulations for regression or continuous validation.
HOW TO USE TEMU
The TEMU Emulator can be used in two main ways:
- Linked with the command line test harness, providing a standalone binary which provides the emulation and simulation environment.
- As a shared library that can be combined or loaded in the corresponding simulation infrastructure or model.
The PLATO Mission
Benefits
Designed for performance
The LLVM based emulator core is highly optimised with different instruction variants, threaded code, and many other sophisticated optimisations. In addition, the spacecraft emulator integrates a dynamic binary translator engine, enabling the direct translation of target instructions to host instructions. Support for custom code patterns detectors, that can trigger either idle mode, or simply call a user provided function, and this can be used for mission specific optimizations.
Instruction-Level Emulation Accuracy
Designed to be used for different use cases, including but not limited to target software development, software validation, and training and operational simulation. The emulator can run in real-time simulation environments. In general existing operating systems and boot software should be able to run unmodified on the emulator thanks to instruction-level accuracy and the extensive I/O model library bundled with TEMU
Highly Customizable
Almost any desired customization is possible through the tailoring mechanisms provided by the Terma Emulator Suite. CPU configurations can be adapted by picking and mapping in different device models as needed , memory remapping can even be triggered dynamically by target software.
Extensible
The emulator has a public API for implementing native device models but can easily be integrated with other device modeling systems (e.g. ECSS-SMP, System-C and others). The emulator has also been designed to allow for additional targets. Any RISC-like (fixed width) instruction-set can be added with relative ease, other non-RISC instruction sets can be supported.
Not Restricted to any Particular Simulation Infrastructure
The Terma Emulator Suite is designed to be embeddable in different simulation frameworks, including to the ESA/SIMSAT software. It is also possible to implement a full simulator using the TEMU framework.
User Friendly
A fully functional command line test harness program provides complete visibility of the emulation to the users. Interactive commands allow the inspection and modification of the memory and emulated registers, assembly and disassembly of instructions, setting of breakpoints and watch points, and more.
Debug Variants Available
The emulator comes in two versions which can be installed at the same time. A normal release version, and a debug version with asserts enabled. The debug version is helpful during simulator integration, but you do not have to pay the performance penalty of runtime asserts if you do not want to.
Exhaustive and Fully Automated Test Suite Enabling Nightly Builds
Each instruction is extensively tested to cover a wide range of possible operands and combinations. The testsuite includes not only instruction tests and functionality, but also real-world uses such as booting the Linux kernel, and several other operating systems. The complete testsuite is executed on every change to the emulator and the emulator release of both continuous builds and tagged versions is predicated on the 100% success of the tests.
Multi-Core and Multi-System Emulation
Multi-core processors (and multi-system emulation) are supported out of the box by the Terma Emulator. Several emulator cores can be run in either in a fully deterministic manner, or in parallel mode offering higher performance but at the cost of full determinism.
Portable
The emulator supports x86-64 Linux, and other POSIX (GNU/Linux, BSD, Solaris, macOS) systems can easily be supported. Windows support can be made available.
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